Semiconductor component and method of manufacture

ABSTRACT

In accordance with an embodiment, a semiconductor component includes a support having a side in which a device receiving structure and an interconnect structure are formed and a side from which a plurality of leads extends. A semiconductor device having a control terminal and first and second current carrying terminals and configured from a III-N semiconductor material is mounted to the device receiving structure. The control terminal of the first electrical interconnect is coupled to a first lead by a first electrical interconnect. A second electrical interconnect is coupled between the first current carrying terminal of the semiconductor device and a second lead. The second current carrying terminal of the first semiconductor device is coupled to the device receiving structure or to the interconnect structure.

The present application is a nonprovisional application of Provisional Patent Application No. 62/196,629 filed on Jul. 24, 2015, by Chun-Li Liu et al., titled “SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE”, which is hereby incorporated by reference in its entirety, and priority thereto for common subject matter is hereby claimed.

TECHNICAL FIELD

The present invention relates, in general, to electronics and, more particularly, to semiconductor structures thereof, and methods of forming semiconductor devices.

BACKGROUND

In the past, semiconductor manufacturers have used a combination of silicon semiconductor materials and III-N semiconductor materials to manufacture cascoded devices, such as a normally-on III-N depletion mode HEMT cascoded with a silicon device. Using this combination of materials helps achieve a normally-off state using a III-N depletion mode device that is normally-on. Cascoded semiconductor devices have been described in U.S. Patent Application Publication Number 2013/0088280 A1 by Rakesh K. Lal et al. and published on Apr. 11, 2013.

After manufacturing cascoded devices from different semiconductor substrate materials, semiconductor component manufacturers typically protect the silicon device and the depletion mode devices in separate packages and connect the devices in the separate packages together via leadframe leads to form a cascode device. A drawback with this approach is that increasing the number of packages increases the cost of a cascoded semiconductor component and degrades the performance of the cascoded devices because of increased parasitics such as parasitic capacitance and parasitic inductance.

Accordingly, it would be advantageous to have a cascoded semiconductor device and a method for manufacturing the cascoded semiconductor device. It would be of further advantage for the structure and method to be cost efficient to implement.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be better understood from a reading of the following detailed description, taken in conjunction with the accompanying drawing figures, in which like reference characters designate like elements and in which:

FIG. 1 is a perspective view of a semiconductor component in a cascode configuration in accordance with an embodiment of the present invention;

FIG. 2 is a cross-sectional view of the semiconductor component of FIG. 1 taken along section line 2-2 of FIG. 1;

FIG. 3 is a bottom view of the semiconductor component of FIGS. 1 and 2;

FIG. 4 is a perspective view of a semiconductor component in a cascode configuration in accordance with another embodiment of the present invention;

FIG. 5 is a perspective view of a semiconductor component in a cascode configuration in accordance with another embodiment of the present invention;

FIG. 6 is a perspective view of a semiconductor component in a cascode configuration in accordance with another embodiment of the present invention;

FIG. 7 is a cross-sectional view of the semiconductor component of FIG. 6 taken along section line 7-7 of FIG. 6;

FIG. 8 is a perspective view of a semiconductor component in a cascode configuration in accordance with another embodiment of the present invention;

FIG. 9 is a perspective view of a semiconductor component in a cascode configuration in accordance with another embodiment of the present invention;

FIG. 10 is a perspective view of a semiconductor component in a cascode configuration in accordance with another embodiment of the present invention;

FIG. 11 is a perspective view of a semiconductor component in a cascode configuration in accordance with another embodiment of the present invention;

FIG. 12 is a cross-sectional view of the semiconductor component of FIG. 11 taken along section line 12-12 of FIG. 11; and

FIG. 13 is a perspective view of a semiconductor component in a cascode configuration in accordance with another embodiment of the present invention.

For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, and the same reference characters in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or anode of a diode, and a control electrode means an element of the device that controls current flow through the device such as a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain n-channel or p-channel devices, or certain n-type or p-type doped regions, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with embodiments of the present invention. It will be appreciated by those skilled in the art that the words during, while, and when as used herein are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as a propagation delay, between the reaction that is initiated by the initial action and the initial action. The use of the words approximately, about, or substantially means that a value of an element has a parameter that is expected to be very close to a stated value or position. However, as is well known in the art there are always minor variances that prevent the values or positions from being exactly as stated. It is well established in the art that variances of up to about ten per cent (10%) (and up to twenty per cent (20%) for semiconductor doping concentrations) are regarded as reasonable variances from the ideal goal of being exactly as described.

DETAILED DESCRIPTION

FIG. 1 is a perspective view of a semiconductor component 10 in accordance with an embodiment of the present invention and FIG. 2 is a cross-sectional view of semiconductor component 10 taken along section line 2-2 of FIG. 1. FIGS. 1 and 2 are described together. What is shown in FIGS. 1 and 2 are a molded device support structure 12 having a top surface 14 and a bottom surface 16. Molded support structure 12 includes a device receiving area 18, a device receiving area 20, and a bond pad 22 at top surface 14 and a contact 24 at bottom surface 16. Device receiving areas 18 and 20 may be referred to as device receiving structures. Device receiving area 18 is configured for receiving a compound semiconductor device such as, for example, a III-nitride device whereas device receiving area 20 is configured for receiving a silicon semiconductor device. In accordance with an embodiment, device receiving area 18, device receiving area 20, and bond pad 22 are substantially coplanar with surface 14. Leadframe leads 26, 28, and 30 protrude from a side or an edge of molded device support structure 12. Molded support structure 12 may be formed by placing an electrically conductive strip in a mold having a mold cavity and injecting a mold compound into the mold cavity. The electrically conductive strip may include pads or plates 18 and 20 that serve as device receiving areas, an interconnect structure 21 that includes bond pad 22 integrally formed with contact 24 through a conductor 25, and a plurality of leadframe leads such as, for example, leadframe leads 26, 28, and 30. After injecting the mold compound into the cavities, the electrically conductive strip may be singulated into a plurality of molded support structures 12. Suitable materials for the electrically conductive strips include copper, aluminum, or the like. As mentioned, molded support structure 12 is illustrated and described as a single element; however, it may be a portion singulated from a leadframe strip encapsulated in a mold compound.

A semiconductor chip 40 is bonded to surface 18A of device receiving area 18 using a die attach material 42, wherein die attach material 42 is an electrically and thermally conductive die attach material. More particularly, surface 44 of semiconductor chip 40 is bonded to surface 18A of device receiving area 18 through electrically insulating die attach material 42. In accordance with an embodiment, semiconductor chip 40 is a compound semiconductor chip having opposing major surfaces 44 and 46, wherein semiconductor chip 40 includes a field effect semiconductor device having a drain contact 50 formed on or from a portion of surface 46, a source contact 52 formed on or from another portion of surface 46, and gate contacts 54 and 55 formed on or from other portions of surface 46. It should be noted that the semiconductor device is not limited to being a field effect transistor. For example, the semiconductor device may be an insulated gate bipolar transistor, a bipolar transistor, a junction field effect transistor, a diode, or the like. In accordance with embodiments in which a discrete semiconductor device such as for example, a field effect transistor, is formed from semiconductor chip 40, semiconductor chip 40 may be referred to as a semiconductor device. In addition, die attach material 42 is not limited to being an electrically conductive material but may be an electrically insulating material or a thermally conductive material. By way of example, semiconductor chip 40 is a III-nitride semiconductor chip, i.e., the substrate material of III-nitride semiconductor chip 40 comprises aluminum nitride. A III-nitride semiconductor material may be referred to as a III-N semiconductor material, a III-nitride based semiconductor material, a III-N based semiconductor material, or the like.

A semiconductor chip 60 is bonded to surface 20A of device receiving area 20 using die attach material 42. In accordance with an embodiment, semiconductor chip 60 is a silicon chip having opposing major surfaces 64 and 66, wherein semiconductor chip 60 includes a vertical field effect semiconductor device having a drain contact 75 formed on or from surface 64, a source contact 72 formed on or from a portion of surface 66, and a gate contact 74 formed on or from another portion of surface 66. Drain contact 75 is bonded to surface 20A of device receiving area 20 through die attach material 42. It should be noted that semiconductor device 60 is not limited to being a vertical field effect transistor or a field effect transistor. For example, the semiconductor device may be an insulated gate bipolar transistor, a bipolar transistor, a junction field effect transistor, a diode, or the like. By way of example, semiconductor chip 60 is a silicon semiconductor chip, i.e., the substrate material of silicon semiconductor chip 40 comprises silicon. A silicon semiconductor material may be referred to as silicon based semiconductor material, a silicon semiconductor material, or the like. In accordance with embodiments in which a discrete semiconductor device such as for example, a field effect transistor, is formed from semiconductor chip 60, semiconductor chip 60 may be referred to as a semiconductor device.

Drain contact 50 of semiconductor device 40 is electrically connected to bond pad 22 through bond wires 76, source contact 52 of semiconductor device 40 is electrically connected to device receiving area 20 through bond wires 78, gate contact 54 of semiconductor device 40 is electrically connected to source contact 72 through a bond wire 80, and gate contact 55 of semiconductor device 40 is electrically connected to leadframe lead 30 through a bond wire 82. Gate contact 74 of semiconductor device 60 is electrically connected to leadframe lead 26 through a bond wire 84, source contact 72 is connected to surface leadframe lead 28 through a bond wire 86 and to leadframe lead 30 through bond wires 88, and drain contact 75 is electrically connected to surface 20A of device receiving area 20 through electrically conductive die attach material 42. It should be noted that gate contact 54 is electrically conducted to gate contact 55 through a metallization system (not shown). Bond wires may be referred to as wirebonds. It should be noted that in accordance with this embodiment semiconductor devices 40 and 60 are electrically connected to device receiving areas 18 and 20, respectively through electrically conductive die attach material 42.

As those skilled in the art are aware, device receiving areas 18 and 20, semiconductor chips 40 and 60, and bond wires 76, 78, 80, 82, 84, 86, and 88 and portions of molded support structure 12 may be encapsulated in a protection material 90 such as, for example a mold compound. It should be noted that leadframe lead 26 serves as a gate leadframe lead or a gate lead, leadframe lead 28 serves as a Kelvin leadframe lead or a Kelvin lead, leadframe lead 30 servers as a source leadframe lead or a source lead, and contact 24 serves as a drain contact.

Thus, semiconductor component 10 includes a III-N cascode switch in which the substrate of the III-N semiconductor material is electrically floating and bond pads are not formed over active regions of semiconductor device 40.

FIG. 3 is a bottom view of semiconductor component 10 in accordance with an embodiment of the present invention. FIG. 3 further illustrates contact 24 and leadframe leads 26, 28, and 30.

FIG. 4 is a perspective view of a semiconductor component 100 in accordance with another embodiment of the present invention. Semiconductor component 100 is similar to semiconductor component 10 except that bond wires 76 have been replaced by an electrically conductive clip 102, bond wires 78 have been replaced by an electrically conductive clip 104, and bond wires 88 have been replaced by an electrically conductive clip 106. It should be noted that mounting semiconductor chips 40 and 60 to device receiving areas 18 and 20, respectively, have been described with reference to FIGS. 1 and 2. Thus, semiconductor component 100 includes a III-N cascode switch in which the substrate of the III-N semiconductor material is electrically floating and bond pads are not formed over active regions of semiconductor device 40.

As those skilled in the art are aware, device receiving areas 18 and 20, semiconductor chips 40 and 60, and bond wires 80, 82, 84, 86, and 88, clips 102, 104, and 106, and portions of molded support structure 12 may be encapsulated in a protection material such as, for example mold compound 90.

FIG. 5 is a perspective view of a semiconductor component 120 in accordance with another embodiment of the present invention. Semiconductor component 120 is similar to semiconductor component 10 except that semiconductor component 120 includes bond wires 122 connecting the semiconductor material of semiconductor chip 60 with surface 18A of device receiving area 18. It should be noted that mounting semiconductor chips 40 and 60 to device receiving areas 18 and 20, respectively, has been described with reference to FIGS. 1 and 2. Bond wires 122 electrically connect source electrode 72, hence the source, of semiconductor device 60 to the body of semiconductor material of semiconductor device 40 through die receiving area 18 and die attach material 42. Thus, semiconductor component 120 includes a III-N cascode switch in which the substrate of the III-N semiconductor material is grounded and bond pads are not formed over active regions of semiconductor device 40.

As those skilled in the art are aware, device receiving areas 18 and 20, semiconductor chips 40 and 60, and bond wires 76, 78, 80, 82, 84, 86, and 88 and portions of molded support structure 12 are typically encapsulated in a protection material such as, for example a mold compound.

FIG. 6 is a perspective view of a semiconductor component 130 in accordance with another embodiment of the present invention. FIG. 7 is a cross-sectional view of semiconductor component 130 taken along section line 7-7 of FIG. 6. FIGS. 6 and 7 are described together. What is shown in FIGS. 6 and 7 are a molded device support structure 132 having a top surface 134 and a bottom surface 136. Molded support structure 132 includes a device receiving area 138, a bond pad 140 at top surface 134, and a contact 143 at bottom surface 136. In accordance with an embodiment, bond pads 138 and 140 are coplanar with surface 134. Leadframe leads 26, 28, and 30 protrude from a side or an edge of molded device support structure 132. Device receiving area 138 may be referred to as a device receiving structure. Molded support structure 132 may be formed by placing an electrically conductive strip in a mold having a mold cavity and injecting a mold compound into the mold cavity. The electrically conductive strip may include a pad or plate 138 having a contact region 140, wherein pad or plate 138 serves as a device receiving area, and a plurality of leadframe leads such as, for example, leadframe leads 26, 28, and 30. After injecting the mold compound into the cavities, the electrically conductive strip may be singulated into a plurality of molded support structures 132. Suitable materials for the electrically conductive strips include copper, aluminum, or the like. As mentioned, molded support structure 132 is illustrated and described as a single element; however, it may be a portion singulated from a leadframe strip encapsulated in a mold compound.

A semiconductor chip 40 is bonded to surface 138A of device receiving area 138 using a die attach material 42I, wherein die attach material 42I is an electrically insulating die attach material. In accordance with an embodiment, semiconductor chip 40 is a compound semiconductor chip having opposing major surfaces 44 and 46, wherein semiconductor chip 40 includes a field effect semiconductor device having a drain contact 50 formed on or from a portion of surface 46, a source contact 52 formed on or from another portion of surface 46, and gate contacts 54 and 55 formed on or from other portions of surface 46. Thus, surface 44 of semiconductor chip 40 is bonded to surface 138A of device receiving area 138 through die attach material 42I. It should be noted that semiconductor device 40 is not limited to being a field effect transistor. For example, semiconductor device 40 may be an insulated gate bipolar transistor, a bipolar transistor, a junction field effect transistor, a diode, or the like. As discussed above, in accordance with embodiments in which a discrete semiconductor device such as for example, a field effect transistor, is formed from semiconductor chip 40, semiconductor chip 40 may be referred to as a semiconductor device.

Drain contact 50 of semiconductor device 40 is electrically connected to surface 138A of device receiving area 138 through bond wires 76, source contact 52 of semiconductor device 40 is electrically connected to leadframe lead 28 through a bond wire 86 and to leadframe lead 30 through bond wires 88, gate contact 54 of semiconductor device 40 is electrically connected to leadframe lead 26 through bond wire 84, gate contact 55 is electrically connected to bond pad 140 through a bond wire 82, and bond pad 140 is electrically connected to leadframe lead 26 through a bond wire 85. In accordance with the embodiment of FIG. 6, leadframe lead 26 is a gate leadframe lead or a gate lead, leadframe lead 28 is a Kelvin leadframe lead or a Kelvin lead, and leadframe lead 30 is a source leadframe lead or a source lead. Bond wires may be referred to as wirebonds. It should be noted that in accordance with this embodiment drain contact 50 of semiconductor device 40 is electrically connected to surface 138A of device receiving area 138. Thus, semiconductor component 130 includes a III-N cascode switch in which the substrate of the III-N semiconductor material is electrically floating and bond pads are not formed over active regions of semiconductor device 40.

As those skilled in the art are aware, device receiving area 138, semiconductor chip 40, and bond wires 76, 82, 84, 86, and 88 and portions of molded support structure 132 are typically encapsulated in a protection material such as, for example mold compound 90.

FIG. 8 is a perspective view of a semiconductor component 139 in accordance with another embodiment of the present invention. Semiconductor component 139 is similar to semiconductor component 130 except that the die attach material of FIG. 8, i.e., die attach material 42, is an electrically and thermally conductive material; and semiconductor component 139 includes bond pad 141 and a bond wire 142, wherein bond wire 142 connects device receiving area 138 with leadframe lead 30 and a bond pad 141 is connected to drain contact 50 through bond wires 76, unlike semiconductor component 130 in which bond wires 76 connect drain contact 50 with device receiving area 138. Bond pad 141 is spaced apart from device receiving area 138. It should be noted that gate leadframe lead 26 is electrically connected to gate electrode 54 via bond wire 84 and to bond pad 140 through bond wire 85. It should be further noted that mounting semiconductor chip 40 to device receiving area 138 has been described with reference to FIGS. 6 and 7. Bond wire 142 electrically connects the substrate of semiconductor chip 40 to source electrode 52 of semiconductor device 40 through leadframe lead 30, hence the source, of semiconductor device 40 is electrically connected to the body of semiconductor material of semiconductor device 40. Thus, semiconductor component 140 includes a discrete III-N field effect transistor in which the substrate of the III-N semiconductor material is grounded and bond pads are not formed over active regions of semiconductor device 40.

As those skilled in the art are aware, device receiving area 138, semiconductor chip 40, and bond wires 76, 82, 84, 85, 86, and 88 and portions of molded support structure 132 are typically encapsulated in a protection material such as, for example mold compound 90.

FIG. 9 is a perspective view of a semiconductor component 150 in accordance with another embodiment of the present invention. Semiconductor component 150 is similar to semiconductor component 100 described with reference to FIG. 4 except the semiconductor device is identified by reference character 40A, i.e., the letter A has been appended to reference character 40, because drain contact 50 has been replaced by a drain contact 50A which extends over a portion of an active area of III-N of semiconductor device 40A and source contact 52 have been replaced by a source contact 52A which extends over another portion of the active area of III-N of semiconductor device 40A. It should be noted that mounting semiconductor chips to device receiving areas has been described with reference to FIGS. 1 and 2. Thus, semiconductor component 150 includes a III-N cascode switch in which the substrate of the III-N semiconductor material is electrically floating and bond pads are formed over active regions of semiconductor device 40A.

As those skilled in the art are aware, device receiving areas 18 and 20, semiconductor chips 40A and 60, and bond wires 80, 82, 84, 86, and 88, clips 102, 104, and 106, and portions of molded support structure 12 are typically encapsulated in a protection material such as, for example mold compound 90.

FIG. 10 is a perspective view of a semiconductor component 160 in accordance with another embodiment of the present invention. Semiconductor component 160 is similar to semiconductor component 120 described with reference to FIG. 5 except that drain contact 50 has been replaced by a drain contact 50B which extends over a portion of an active area of III-N of semiconductor device 40B, source contact 52 has been replaced by a source contact 52B which extends over another portion of the active area of III-N of semiconductor device 40B, and gate contacts 54 and 55 have been replaced by a gate contact 54B which extends over another portion of the active area of III-N semiconductor device 40B, bond wire 80 has been replaced by bond wires 80B, and bond wire 82 is not present in the embodiment of FIG. 10. A reference character B has been appended to reference character 40 to distinguish a semiconductor chip having bond pads over active areas from a semiconductor chip without bond pads over active areas. It should be noted that mounting semiconductor chips to device receiving areas has been described with reference to FIGS. 1 and 2. Thus, semiconductor component 160 includes a III-N cascode switch in which the substrate of the III-N semiconductor material is electrically grounded and bond pads are formed over active regions of semiconductor device 40B.

As those skilled in the art are aware, device receiving areas 18 and 20, semiconductor chips 40B and 60, and bond wires 76, 78, 80B, 84, 86, 88, and 122, and portions of molded support structure 12 are typically encapsulated in a protection material such as, for example a mold compound.

FIG. 11 is a perspective view of a semiconductor component 170 in accordance with another embodiment of the present invention. FIG. 12 is a cross-sectional view of semiconductor component 170 taken along section line 12-12 of FIG. 11. FIGS. 11 and 12 are described together. What is shown in FIGS. 11 and 12 are a molded device support structure 132 that includes device receiving area 138 and bond pad 140, and leadframe leads 26, 28, and 30. Molded device support structure 132 has been described with reference to FIGS. 6 and 7.

A semiconductor chip 40B is bonded to surface 138A of device receiving area 138 using a die attach material 42I, wherein die attach material 42I is an electrically insulating die attach material. Thus, surface 44 is bonded to surface 138A of device receiving area 138 through an electrically and thermally conductive die attach material 42I. In accordance with an embodiment, semiconductor chip 40B is a compound semiconductor chip having opposing major surfaces 44 and 46, wherein semiconductor chip 40B includes a field effect semiconductor device having a drain contact 50B formed on a portion of an active area of semiconductor device 40B, a source contact 52B formed on another portion of the active area of semiconductor device 40B, and a gate contact MB formed on another portion of the active area of semiconductor device 40B. Semiconductor device 40B has been described with reference to FIG. 10.

Drain contact 50B of semiconductor device 40B is electrically connected to device receiving area 138 through bond wires 76, source contact 52B of semiconductor device 40B is electrically connected to leadframe lead 28 through a bond wire 86 and to leadframe lead 30 through bond wires 88, gate contact MB of semiconductor device 40B is electrically connected to leadframe lead 26 through bond wire 84. Bond pad 140 is electrically connected to leadframe lead 26 through a bond wire 172 and to gate contact MB through bond wire 83. In accordance with the embodiment of FIGS. 11 and 12, leadframe lead 26 is a gate leadframe lead or a gate lead, leadframe lead 28 is a Kelvin leadframe lead or a Kelvin lead, and leadframe lead 30 is a source leadframe lead or a source lead. Bond wires may be referred to as wirebonds. It should be noted that in accordance with this embodiment drain contact 50B of semiconductor device 40B is electrically connected to surface 138A of device receiving area 138 by bond wire 172. Thus, semiconductor component 170 includes a III-N cascode switch in which the substrate of the III-N semiconductor material is electrically floating and bond pads are formed over active regions of semiconductor device 40B.

FIG. 13 is a perspective view of a semiconductor component 180 in accordance with another embodiment of the present invention. Semiconductor component 180 is similar to semiconductor component 139 except that semiconductor chip 40 of FIG. 8 has been replaced by a semiconductor chip 40B (shown in FIG. 11); semiconductor component 180 includes a bond pad 141 shown and described with reference to FIG. 8; bond wire 85 of semiconductor component 139 is replaced by a bond wire 172; and a bond wire 84 connects gate contact 54B to bond pad 140. Thus, drain contact 50B is electrically connected to bond pad 141 by bond wires 76, source contact 52B is electrically connected to lead 30 by bond wires 88 and to lead 28 by bond wire 86, and gate contact 54B is electrically connected to bond pad 140 by a bond wire 84 and to lead 26 by a bond wire 84. Bond wire 142 connects leadframe lead 30 with surface 138A of device receiving area 138. Bond wires 142 and 88 and lead 30 electrically connect source electrode 52B, hence the source of semiconductor device 40B, to the substrate of the semiconductor material of semiconductor device 40B. Thus, semiconductor component 180 includes a III-N cascode switch in which the substrate of the III-N semiconductor device is connected to its source and bond pads are formed over active regions of semiconductor device 40B. The source of the III-N semiconductor device can be connected to a potential such as, for example ground. Connecting the source of the III-N semiconductor device also connects the substrate of the III-N semiconductor device to ground in accordance with this embodiment.

Although certain preferred embodiments and methods have been disclosed herein, it will be apparent from the foregoing disclosure to those skilled in the art that variations and modifications of such embodiments and methods may be made without departing from the spirit and scope of the invention. It is intended that the invention shall be limited only to the extent required by the appended claims and the rules and principles of applicable law. 

What is claimed is:
 1. A semiconductor component having at least first and second terminals, comprising: a support having first and second sides and a plurality of leads, the first side of the support having a first device receiving structure, a second device receiving structure, and a first interconnect structure and the second side of the support having a contact; a first semiconductor device mounted to the first device receiving structure, the first semiconductor device having a control terminal and first and second current carrying terminals and configured from a III-N semiconductor material; a first electrical interconnect coupled between the control terminal of the first semiconductor device and a first lead of the plurality of leads; a second electrical interconnect coupled between the first current carrying terminal of the first semiconductor device and the first interconnect structure; and a third electrical interconnect coupled between the second current carrying terminal of the first semiconductor device and the second device receiving structure.
 2. The semiconductor component of claim 1, wherein the first semiconductor device is a gallium nitride semiconductor device.
 3. The semiconductor component of claim 1, further including a fourth electrical interconnect coupled between the control terminal of the first semiconductor device and a second lead of the plurality of leads.
 4. The semiconductor component of claim 3, wherein the first electrical interconnect is a bond wire, the second electrical interconnect is a bond wire, and the third electrical interconnect is a bond wire.
 5. The semiconductor component of claim 1, further including a second semiconductor device mounted to the second device receiving structure, the second semiconductor device having a control terminal and first and second current carrying terminals and configured from a silicon semiconductor material.
 6. The semiconductor component of claim 5, further including: a fourth electrical interconnect coupling the control terminal of the second semiconductor device and a third lead of the plurality of leads; and a fifth electrical interconnect coupled between the first current carrying terminal of the second semiconductor device and the first lead of the plurality of leads, wherein the first current carrying terminal of the second semiconductor device is coupled to the control terminal of the first semiconductor device by the first electrical interconnect.
 7. The semiconductor component of claim 6, further including a seventh electrical interconnect coupled between the first current carrying terminal of the second semiconductor device and a second lead of the plurality of leads.
 8. The semiconductor component of claim 7, further including an eighth electrical interconnect coupled between the first semiconductor component receiving structure and the first current carrying terminal of the second semiconductor device.
 9. The semiconductor component of claim 4, wherein the first current carrying terminal of the first semiconductor device and the second current carrying terminal of the first semiconductor device are over active regions of the first semiconductor device.
 10. A semiconductor component, comprising: a first device receiving structure, the first device receiving structure embedded in a mold compound; a first bond pad embedded in the mold compound: a plurality of leadframe leads extending from the mold compound; a first semiconductor device bonded to the first device receiving structure, the first semiconductor device having a control electrode, a first current carrying electrode, and a second current carrying electrode; a first electrical interconnect coupling a first leadframe lead to the first current carrying electrode of the first semiconductor device; and a second electrical interconnect coupling a second leadframe lead to the control electrode of the first semiconductor device.
 11. The semiconductor component of claim 10, further including: a third electrical interconnect coupling the second current carrying electrode to the first device receiving structure; and a fourth electrical interconnect coupling a third leadframe lead to the first current carrying electrode of the first semiconductor device.
 12. The semiconductor component of claim 11, further including: a fifth electrical interconnect coupling the first bond pad to the control electrode of the first semiconductor device; and a sixth electrical interconnect coupling the first bond pad to the third leadframe lead.
 13. The semiconductor component of claim 12, further including a seventh electrical interconnect coupling the first leadframe lead to the first device receiving structure.
 14. The semiconductor component of claim 11, further including: a fifth electrical interconnect coupling the control electrode of the first semiconductor device to the first leadframe lead; a sixth electrical interconnect coupling the first leadframe lead to the first device receiving structure; and a seventh electrical interconnect coupling the first bond pad to the first current carrying electrode of the first semiconductor device.
 15. The semiconductor component of claim 10, wherein the control electrode, the first current carrying electrode, and the second current carrying electrode of the first semiconductor device are over an active area of the first semiconductor device, and wherein the first semiconductor device is a III-N semiconductor device.
 16. The semiconductor component of claim 10 further including: a second device receiving structure, the second device receiving structure embedded in a mold compound; a second semiconductor device bonded to the second device receiving structure, the second semiconductor device having a control electrode, a first current carrying electrode, and a second current carrying electrode; a third electrical interconnect coupling the second current carrying electrode of the second semiconductor device to the first bond pad; a fourth electrical interconnect coupling the first current carrying electrode to the first device receiving structure; and a fifth electrical interconnect coupling the control electrode of the second semiconductor device to the second current carrying electrode of the first semiconductor device.
 17. The semiconductor component of claim 16, further including a sixth electrical interconnect coupling the control electrode of the second semiconductor device to the first leadframe lead.
 18. The semiconductor component of claim 17, further including a seventh electrical interconnect coupling the second device receiving structure to the first current carrying electrode of the first semiconductor device.
 19. The semiconductor component of claim 18, wherein the first electrical interconnect is one of bond wire or a clip, the second electrical interconnect is one of a bond wire or a clip, and the third electrical interconnect is one of a bond wire or a clip.
 20. A method for manufacturing a semiconductor component, comprising: forming a support having first and second sides and second sides that are parallel to each other and a third side that is perpendicular to the first side and the second side, wherein the support has a plurality of leads extending from the third side and a device receiving structure extending from the first side into the support; mounting a first semiconductor device to the first device receiving structure, the first semiconductor device having a control terminal and first and second current carrying terminals and configured from a III-N semiconductor material; electrically coupling the control terminal of the first semiconductor device to a first lead of the plurality of leads; electrically coupling first current carrying terminal of the first semiconductor device to a second lead of the plurality of leads; and electrically coupling the second current carrying terminal of the first semiconductor device to one of the first device receiving structure or the first interconnect structure. 